The signal propagation delay time increases as the signal path length through a network increases. The propagation delay time is also relatively higher for a signal transmitting across a "heavily-loaded" network (i.e., a network or net with a large capacitive load), since the large capacitive load increases the RC delay time of the propagating signal. One example of a heavily-loaded net is an SRAM word line.
As feature sizes decrease, the metal layers in integrated circuits increase in resistance value. The higher resistance values increase the RC delay for signals transmitting across the nets formed in the metal layers.
The microprocessor cycle time increases if the propagation delay time increases for signals processed by the microprocessor. Additionally, timing requirements in "critical nets" ("critical paths") may also not be met if signal propagation delay time increases along a critical net.
According to conventional approaches, repeaters, normally in the form of inverters, may be inserted in a long net to increase the signal propagation speed. The repeaters divide the long net into multiple shorter-length nets wherein each repeater drives one of the shorter length nets. In many instances, the desired signal timing (or optimized timing) is attained by insertion of an odd number of inverters. However, the odd number of inverters reverses the polarity (voltage swing) of the propagating signal. To obtain the original polarity of the propagating signal, an additional inverter is inserted in the net so that an even number of inverters is implemented. However, the additional inverter adds delay and, as a result, the desired signal timing constraint (or optimized timing value) may not be satisfied for the net.
Conventional approaches also have the "neighbor effect" problem. The neighbor effect occurs when signals propagating along neighboring nets switch in opposite directions. The neighbor effect leads to a higher effective switching capacitance that also increases the signal propagation delay time.
Accordingly, it is desirable to provide a method and apparatus that can increase the propagation speed of a signal across a net in an integrated circuit and that can overcome the above mentioned deficiencies of conventional approaches.
An important case of the RC delay problem is a net driven by one of the multiple drivers attached to the net. The net cannot use repeaters because repeaters, being unidirectional, disallow the drivers to reach all portions of the net. An example of such net is the result bus of a multiple functional unit. It is desirable to provide a method and apparatus that improve the propagation delay in this case. The conventional approach to solve this case is the use of a bi-directional repeater. However the bi-directional repeater is slow and requires a control circuit to direct the direction of the signal flow. The control circuit is likely to not only be costly in terms of area, but also can introduce speed problems by itself.